1. Field of the Invention
The present invention relates to an apparatus, method and computer program product for design verification of semiconductor integrated circuits. More specifically, the present invention relates to power supply variation analysis and delay variation calculation based on power supply variations.
2. Description of the Related Art
In recent years, there are remarkable technology progresses in power supply voltage reduction and operation speed enhancement of semiconductor integrated circuits. On the other hand, the power supply voltage reduction and operation speed enhancement, as well as the increase in the interconnection resistance due to the reduction in dimensions of layout patterns, lead to the situation in which the variations in the power supply voltage are not negligible for ensuring the stable operations of the semiconductor integrated circuit.
Recently, attention is paid to power supply variation analysis for power supply noise, that is, variations in the power supply voltage and the ground voltage caused by semiconductor integrated circuit operations. For example, Lin et al. discloses a vectorless dynamic power-ground noise analysis approach in a non-patent document entitled: S Lin, M. Nagata, K. Shimazaki, K. Satoh, M. Sumita, H. Tsujikawa, A. T. Yang, “Full-chip Vectorless Dynamic Power Integrity Analysis and Verification Against 100 uV/100 ps-Resolution Measurement”, Proceedings of Custom Integrated Circuits Conference 2004, October 2004, Pp. 509-512. In the power supply variation analysis, variations in the power supply voltage and the ground voltage are calculated for desired one(s) of instances integrated within in the semiconductor integrated circuit.
In FIG. 5, typical models of power supply variation analysis are shown. In FIG. 5, instances A and B are instances incorporated within an integrated circuit for which the power supply variation analysis is to be performed. The output signals of the respective instances vary in response to signal level changes of the respective input signals. The signal level changes in the output signals cause generation of power supply currents through the power and ground lines, and the power supply currents cause variations in the voltage levels of the power and ground lines due to the resistances thereof. When the resistances of the power and ground lines of the instance B are larger than those of the instance A, the instance B experiences larger power supply variations. The magnitude of the power supply variations depends not only on the resistance of the power and ground lines but also by the buffer's drive capability, the output load capacitance, the slew rate of the input signal, the capacitance between the power and ground lines, and so on. The power supply variation analysis needs to be performed in light of these various factors.
One issue is that the analysis time necessary for power supply variation analysis undesirably increases as the increase in the integrated circuit scale, when the variations in the power supply voltage are analyzed for all instances integrated within the integrated circuit.
Also, one proposed approach for the reduction of the power supply variations is to integrate decoupling capacitors (or capacitor cells) within the integrated circuit. However, this approach suffers from the increase in the calculation time for determining the positions and capacitances of the decoupling capacitors.
Japanese Laid-Open Patent Application No. 2005-4268 (referred to as the '268 application, hereinafter) discloses a conventional method and apparatus for power supply variation analysis. A description is given of the disclosed method and apparatus in the following, referring to FIGS. 24 and 25.
FIG. 24 is a flowchart showing the power supply variation analysis method disclosed in the '268 application. The disclosed method is directed to calculation time reduction of the power supply variation analysis by dividing the voltage calculation range, which is defined as the time period between the switching of the input signal Vin and the switching of the output signal Vout, into multiple time segments, by averaging or characterizing the voltage waveforms in the respective time segments.
A description is given next of the configuration of the power supply variation analysis apparatus disclosed in the '268 application, referring to FIG. 25. FIG. 25 is a block diagram of the conventional power supply variation analysis apparatus. Layout data of the target LSI (large scale integrated circuit) are generated by the placement and routing section 101 and circuit connection data extracted from the layout data are fed to a power supply variation analysis section 102. The power supply variation analysis section 102 analyzes the power supply variations to generate power supply variation report data 103 indicative of the power supply variations. The power supply variation report data 103 is fed to a delay calculation section 104. The delay calculation section 104 performs delay calculation and outputs SDF (standard delay format) data which are circuit delay data associated with circuit blocks for which STA (static timing analysis) is to be performed later. The SDF data are inputted to an STA (static timing analysis) section 105, and the STA section 105 generates timing report data 106. The timing report data 106 is fed to an optimization section 107, and the optimization section 107 performs circuit optimization.
Furthermore, Japanese Laid-Open Patent Application No. 2000-99554 (referred to as the '554 application, hereinafter) discloses an example of a delay library used for the power supply variation analysis. In detail, the '554 application discloses that buffer delay times are expressed in the delay library with three parameters: the slew rate of the input signal, the output load capacitance, and the power supply voltage.
The '554 application also discloses a integrated design technique which involves obtaining operating voltage distributions of the respective logic blocks depending on the positions of the power supply lines, performing initial schematic placement of the logic blocks, calculating the delay times of the respective logic blocks using the delay library, performing schematic placement of the logic blocks again so as to reduce the calculated delay time for the improvement of the operation timings of the logic blocks, and then performing detailed placement of the logic blocks.
In the conventional techniques (such as the technique disclosed in the '268 application), delay calculation is followed by timing analysis based on the delay calculation result. This is followed by cell arrangement optimization based on the timing analysis result, such as insertion of capacitor cells or movement of instances, when any timing error is discovered by the timing analysis. This undesirably necessitates performing the power supply variation analysis and timing analysis again after the cell arrangement optimization to determine whether the problem is solved by the cell arrangement optimization. This approach undesirably requires a longer time for converging the calculation result.
Furthermore, an operation of a certain circuit may cause a malfunction of another circuit when the integrated circuit suffers from large power supply voltage variations; however, such malfunction is often overlooked by ordinary static timing verification. The above-described conventional techniques give no considerations to this problem.